FPGA and RTL design
Logic for FPGAs written in SystemVerilog or VHDL, verified in simulation before it reaches the board.
01 · Build
What we build
When a processor cannot keep up, the work moves into logic: capture at gigasamples per second, a custom interface, a filter that must finish every cycle.
- RTL in SystemVerilog or VHDL for AMD Xilinx and Intel Altera FPGAs
- Testbenches in cocotb and UVM, with coverage reports on every commit
- Timing closure with written constraints and recorded margins
- AXI4, PCIe, Ethernet MAC and MIPI CSI-2 interfaces, and high-speed ADC capture
- Linux drivers and device-tree entries for the logic on Zynq and Agilex SoCs
- Reproducible bitstream builds in CI with Vivado, Quartus and Verilator
02 · Demo · sample data
Try it live.
A working sample with made-up data. It runs in your browser; nothing is sent anywhere.
rtl@build:~/adc_capture$ make sim TOP=adc_capture verilator: building obj_dir/Vadc_capture cocotb: 14 tests collected rtl@build:~/adc_capture$ make test
03 · Features
What it does well
- 01
Simulation first
Every block is exercised in simulation with known stimulus before it is placed on a board.
- 02
Coverage reports
Functional and code coverage are measured per block, so untested states are visible.
- 03
Recorded timing
Slack on every clock domain is recorded per build, so a change that eats margin is caught.
- 04
Clock-domain checks
Every crossing between clocks is listed and synchronised, and checked by the tools.
- 05
Resource budgets
LUT, block RAM and DSP use is tracked per build against the part you chose.
- 06
Hardware in the loop
The same tests run against the board over JTAG or Ethernet once the logic is loaded.
04 · FAQ
Questions
Do we need an FPGA, or will a microcontroller do?
Often a microcontroller is enough, and it is simpler to maintain. An FPGA earns its place when timing must be exact to the clock cycle, when data arrives faster than software can read it, or when you need many interfaces in parallel. We say which, with the reasoning, before any design work.
Can you take over an existing FPGA design?
Yes. We first rebuild it from source and confirm the bitstream matches what ships, then add a testbench around the parts that change. If the original constraints or simulation files are missing, we recreate them before modifying any logic.
Which tools and parts do you use?
Vivado for AMD Xilinx parts such as Artix, Kintex and Zynq UltraScale+, and Quartus Prime for Intel Altera parts such as Cyclone and Agilex. For simulation we use Verilator, GHDL or the vendor simulator, driven by cocotb or UVM testbenches.
05 · Services
Services that go with it
06 · Software
Related software
- SoftwareEmbedded firmwareDependable code for the microcontrollers inside your product, from first board bring-up to updates in the field.
- SoftwareDevice driversKernel and user-mode drivers that let an operating system talk to your own hardware safely and quickly.
- SoftwareSafety-critical softwareEmbedded C written to MISRA C and traced from requirement to test, ready for a functional-safety assessment.
- SoftwareCompilers and runtimesLanguages, compilers and runtimes that turn your rules, formulas or scripts into fast, checked code.